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Canaan Inc. /K210 /SYSCTL /clk_en_peri

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Interpret as clk_en_peri

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (rom_clk_en)rom_clk_en 0 (dma_clk_en)dma_clk_en 0 (ai_clk_en)ai_clk_en 0 (dvp_clk_en)dvp_clk_en 0 (fft_clk_en)fft_clk_en 0 (gpio_clk_en)gpio_clk_en 0 (spi0_clk_en)spi0_clk_en 0 (spi1_clk_en)spi1_clk_en 0 (spi2_clk_en)spi2_clk_en 0 (spi3_clk_en)spi3_clk_en 0 (i2s0_clk_en)i2s0_clk_en 0 (i2s1_clk_en)i2s1_clk_en 0 (i2s2_clk_en)i2s2_clk_en 0 (i2c0_clk_en)i2c0_clk_en 0 (i2c1_clk_en)i2c1_clk_en 0 (i2c2_clk_en)i2c2_clk_en 0 (uart1_clk_en)uart1_clk_en 0 (uart2_clk_en)uart2_clk_en 0 (uart3_clk_en)uart3_clk_en 0 (aes_clk_en)aes_clk_en 0 (fpioa_clk_en)fpioa_clk_en 0 (timer0_clk_en)timer0_clk_en 0 (timer1_clk_en)timer1_clk_en 0 (timer2_clk_en)timer2_clk_en 0 (wdt0_clk_en)wdt0_clk_en 0 (wdt1_clk_en)wdt1_clk_en 0 (sha_clk_en)sha_clk_en 0 (otp_clk_en)otp_clk_en 0 (rtc_clk_en)rtc_clk_en

Description

Peripheral clock enable

Fields

rom_clk_en
dma_clk_en
ai_clk_en
dvp_clk_en
fft_clk_en
gpio_clk_en
spi0_clk_en
spi1_clk_en
spi2_clk_en
spi3_clk_en
i2s0_clk_en
i2s1_clk_en
i2s2_clk_en
i2c0_clk_en
i2c1_clk_en
i2c2_clk_en
uart1_clk_en
uart2_clk_en
uart3_clk_en
aes_clk_en
fpioa_clk_en
timer0_clk_en
timer1_clk_en
timer2_clk_en
wdt0_clk_en
wdt1_clk_en
sha_clk_en
otp_clk_en
rtc_clk_en

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data